With the advancement of technology, submicron CMOSonly process is available now for
Application Specific Integrated Circuits (ASICs). The high integration leads to the need for
high pin counts. However voltage supply and ground bounce due to many output drivers
switching at the same time is becoming a major problem. In...
Synchronization is one of the important issues in digital system design. While
other approaches have been intriguing, up until now a globally clocked timing
discipline has been the dominant design philosophy. However, we have reached the
point, with advances in technology, where other options should be given serious
consideration. VLSI...
Computer has evolved rapidly during the past several decades in terms of
its implementation technology; it's architecture, however, has not changed dramatically
since the von Neumann computer(control flow) model emerged in the 1940s. One
main reason is that the performance for this kind of computers was able to satisfy
the...
A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as
an asynchronous storage element in micropipelines or a part of the synchronizer. It is
capable of double-edge triggering which latches data at both the rising and the trailing
edges. It is also free of the...
The recent advances in VLSI technology have facilitated feature shrinking
and hence a rapid increase in the levels of integration at the chip level. This increase
in the level of integration has brought along with it a host of other constraints, the
most crucial being timing management and increased power...
A VLSI system for image compression based on two dimensional discrete cosine transform
(2-D DCT) is designed and its performance is estimated. The focus is mainly on the reduction
of power consumption and a reasonable speed. A 2-D DCT algorithm called row-column
decomposition is chosen for the VLSI design of...
The objective of this thesis is to design a high speed digital FIR filter. The inputs of the
system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs,
multiplies them with their coefficients and adds the results. The main design task is to
take the input data, which...
Asynchronous circuits have recently been a breakthrough in many high performance computers. The concept of asynchronous circuits which started a long time ago has slowly grasped the attention of many designers. The Muller-C-element is an important control block in many asynchronous designs and therefore it is important to understand some...
A relatively recent development in the late 1980s in processors has been the superscalar processor. Superscalar processors use multiple pipelines in an attempt to achieve higher performance than previous generations of processors. Having multiple pipelines makes it possible to execute more than one instruction per cycle. However, since instructions are...
Better performance has been one of the main motivations behind the recent resurgence
of interest in asynchronous circuits (no matter whether this is always true or not).
We are particularly interested in the performance of pipelines since they are used extensively
in current digital systems. There exists an algorithm that...
A Graphic User Interface is developed to determine the existence of a
particular sequence of piano notes within a monophonic sound waveform.
Such waveforms are recorded within the Graphic User Interface and then
passed to the monophonic analysis engine. The first phase of analysis segments
the PCM sound data to...
The counterflow pipeline concept was originated by Sproull et. al.[1] to demonstrate the concept of asynchronous circuits. The basic premise is that a simple architecture with only local communication and control and a simple regular structure will result in increased performance. This thesis attempts to analyze the performance of the...
Sorting is one of the more computationally intensive tasks a computer performs. One of the most effective ways to speed up the task of sorting is by using parallel algorithms. When implementing a parallel algorithm, the designer has to make several decisions. Among the decisions are the algorithm and the...
The counterflow pipeline concept was originated by Sproull and Sutherland to demonstrate
the concept of asynchronous circuits. This architecture relies on distributed decision
making and localized clocking and data movement. We have taken these ideas and reformulated
them into a substantially faster more scalable architecture that has the same distributed...
Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area.
In...
Currently, the two most critical factors of microprocessor design are performance and power. The optimum balance of these two factors is reflected in the speed-power product(SPP). 32-bit CMOS adders are used as representative circuits to investigate a method of
reducing the SPP. The purpose of this thesis is to show...
With the success of the CounterDataFlow Pipeline microarchitecture developed by Oregon State University, there is increasing demand for a highly flexible high-level simulator modeling tool to support the further expansions and studies of the Counterflow pipeline processors family. This work examines the implementation of a Java-based execution-driven simulator modeling tool,...
Power optimization becomes more and more important due to the design cost and reliability. Sometimes high power consumption means expensive package cost and low reliability. The first step in optimizing power consumption is determining where power is consumed within a processor. While system-level code tracing and bit transition calculation are...
Internet appliances at home are still at the beginning stage of development now. Many solutions are provided to connect those home appliances on net by wireless way or through wire. However, this thesis only focuses on the key issue of internet appliances, which is connectivity symbolized by the TCP/IP layer...
Traditionally sinusoidal signal generation has been implemented with purely analog circuits such as phase-locked loops. The alternative of using a digital system to perform this signal generation has previously been unattractive due to limitations in clock frequency and size. However, recent advancements in sub-micron fabrication techniques have made the digital...
Digital systems, in particular microprocessor, have recently experienced phenomena growth in performance. Both technology advancement and clever design have sustained this performance growth. As clock frequency heads into the Ghz range, new circuit design, for both logic and storage, are needed. Such new circuit technology must provide needed performance with...
This thesis will discuss two critical components of a digital system -- domino logic styles and flip-flops. In today's microprocessors, both domino logic and flip-flops are essential to high-performance and low-power design. Two new domino logic styles are presented and analyzed, Double Edge Triggered (DET) and Double Data Rate (DDR)...
This research develops an object-oriented approach of modeling microprocessor architecture. A generic modeling library, bBlocks, is proposed as a framework for constructing microprocessor simulation. bBlocks is a collection of predefined abstract components (blocks) implemented in Java, the object-oriented programming language. Blocks are defined and used as the basic components in...
Current superscalar microprocessors' performance depends on its frequency and the
number of useful instructions that can be processed per cycle (IPC). Higher frequency
is achieved with process advancement, new circuit techniques, and microarchitectural
improvement. Number of instructions processed per cycle depends mainly on
microarchitecture techniques that exploit parallelism both spatially...
The wakeup logic in out-of-order superscalar microprocessors is responsible for resolving the data dependency hazard between instructions. Its performance is critical because it may prevent the processor to have deeper pipelines or to achieve the highest IPC (Instructions Per Cycle) possible. In this thesis, we implemented the circuit and layout...
While the performance gap between microprocessors and main memory is ever increasing each year, cache memory has been a bridge to alleviate this discrepancy. In this thesis proposal, we introduce three techniques to tolerate this processor and memory speed imbalance. First, we propose the bloom filter scheme to identify which...
This thesis investigates an implementation of speech recognition front-end. It is an application specific integrated circuit (ASIC) solution. A Mel Cepstrum algorithm is implemented for the feature extraction. We present a new mixed split-radix and radix-2 Fast Fourier Transform (FFT) algorithm, which can effectively minimize the number of complex multiplications...
Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic circuits have significantly higher speed and lower area compared to static circuits for performing similar operations. Register File (RF) arrays are located at the top...
In modern on-chip memories, an increasing demand for higher performance, lower power, reduced area, and improved robustness creates a rising need for advanced microarchitecture and circuit design techniques. Particularly in large-signal multi-ported register files, these advanced design techniques include: (i) multi-banked arrays, (ii) multi-frequency arrays, (iii) multi-bit width gating, (iv)...
Ferrites have been used for various high frequency applications as bulk
materials. These applications, however, are limited to large dimension devices. In
this thesis, thin film ferrites were deposited from a low temperature solution-based
deposition process that is suitable for micro-scale high frequency applications. The
low temperature nature of this...