The rapid development of semiconductor technology and the increasing complexity of VLSI chips have prompted both the industry and the
academic community alike to take an indepth look at the VLSI design
problem. Many design methodologies have been proposed and associated
computer-aided tools developed. This thesis is a study of...
Minimizing the number of product terms in a PLA implementation is a large step
towards saving area on a VLSI chip using PLA logic. Due to the large amounts of computer
time necessary to achieve this minimization, a number of heuristic approaches have
been developed to provide near-optimal solutions in...
Sorting is typically a compute intensive operation used in many
areas of industry. With improved technology, both in the VLSI and CAE
areas, we can afford to develop hardware based database computers to
move the work load off the main computer. In this thesis the
architecture of a VLSI parallel...
This thesis is concerned with the development of a unique
parallel sort-merge system suitable for implementation in VLSI.
Two new sorting subsystems, a high performance VLSI sorter and a
four-way merger, were also realized during the development
process. In addition, the analysis of several existing parallel sorting
architectures and algorithms...
In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed
and developed. Using multi-coordinate systems (MCS), a unified theory for mapping
algorithms from their original algorithmic specifications onto multi-rate arrays is
developed.
A multi-rate array is a grid of processors in which each interconnection may have its
own...
Current trends in integrated circuit technology are continuing towards physically smaller components and related structures. Interconnects between circuit components have reached sub-micron dimensions which can not be modeled accurately by the current ideal microstrip analysis based techniques. These techniques often assume that the structure being modeled is perfectly conducting, smooth,...
The new CMOS folded source-coupled logic (FSCL)
technique intended for mixed-mode integrated circuits has
been designed. It has advantages over conventional CMOS
circuit in terms of reduced current spike, circuit delay,
logic flexibility, and layout density. A simple CPU
implemented in 2 μm CMOS technology with a 5.0 volt supply...
A series of complex digital blocks have been designed and fabricated using the newly
developed current-mode differential CMOS logic family viz. the Folded Source-Coupled
Logic ( FSCL ). The main feature of this logic family is the low current spikes generated
during the switching transitions ( at least 2 orders...
Layered multiconductor coupled slot and strip-slot structures are characterized by introducing the full-wave modal analysis as well as the quasi-TEM spectral domain technique. In the modal analysis, the electric and magnetic fields are constructed in terms of modal fields in different regions. Application of the boundary conditions at interfaces for...
Fully efficient systolic arrays for the solution of Toeplitz
matrices using Schur algorithm [1] have been obtained. By applying
clustering mapping method [2], the complexity of the algorithm is
0(n) and it requires n/2 processing elements as opposed to n
processing elements developed elsewhere [1].
The motivation of this thesis...
Synchronization is one of the important issues in digital system design. While
other approaches have been intriguing, up until now a globally clocked timing
discipline has been the dominant design philosophy. However, we have reached the
point, with advances in technology, where other options should be given serious
consideration. VLSI...
Error correction codes (ECCs) have been widely used in communication systems and storage devices. Nowadays, the rapid development of integrated circuit technologies makes feasible the implementation of powerful ECCs such as turbo code and low-density parity-check (LDPC) code. However, these high-performance codes require complex decoding algorithms, resulting in large hardware...
Nowadays, error correction codes have become an integral part in almost all the modern digital communication and storage systems. With the continuously increasing demands for higher speed and lower power communication systems, efficient VLSI implementations of those error correction codes have great importance for practical applications. In this thesis, several...
This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail....
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. It is...