A computationally efficient and accurate substrate noise coupling model for multiple contacts in heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for...
A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-μm quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD)...
A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of...
This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case)...
The parasitic components of MOS switches at high speeds affect the linearity and resolution of CMOS sample and hold circuits. CCD-based circuit design can offer good performance at high speeds. This thesis presents the design of sample and hold circuits using charge-coupled device structures in a standard CMOS process. Three...
This thesis presents distinctly different methods of accurately predicting phase noise and absolute jitter in ring oscillators. The phase noise prediction methods are the commercially available SpectreRF and isf_tool, a simulator developed in this work from the Hajimiri and Lee theory of phase noise. Absolute jitter due to deterministic supply...
An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is presented. It is shown that the ESD structures degrade LNA performance particularly for higher frequency applications. Two LNAs, one with ESD protection and one without,...
In this dissertation, a new Δ∑ A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantization noise gain while maintaining stable operation and thus achieve 14-bit resolution at 8 times oversampling. A fifth-order...