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  • Failure analysis of Muller-C-element

    Creator:
    Chew, Oonpin
    Abstract:
    Asynchronous circuits have recently been a breakthrough in many high performance computers. The concept of asynchronous circuits which started a long time ago has slowly grasped the attention of many designers. The Muller-C-element is an important control block in many asynchronous designs and therefore it is important to understand some...
    Resource Type:
    Masters Thesis
    Full Text:
    devices. This problem is even more prominent in an asynchronous circuit because individual blocks are

  • Performance modeling and analysis of asynchronous pipelines for designers

    Creator:
    Chang, Chih-ming, 1964-
    Abstract:
    Better performance has been one of the main motivations behind the recent resurgence of interest in asynchronous circuits (no matter whether this is always true or not). We are particularly interested in the performance of pipelines since they are used extensively in current digital systems. There exists an algorithm that...
    Resource Type:
    Dissertation
    Full Text:
    Number Of Stages 123 6.6 Summary 125 7. PERFORMANCE EVALUATION OF TWODIMENSIONAL ASYNCHRONOUS PIPELINES

  • A microarchitecture study of the counterflow pipeline principle

    Creator:
    Janik, Kenneth J.
    Abstract:
    The counterflow pipeline concept was originated by Sproull et. al.[1] to demonstrate the concept of asynchronous circuits. The basic premise is that a simple architecture with only local communication and control and a simple regular structure will result in increased performance. This thesis attempts to analyze the performance of the...
    Resource Type:
    Dissertation
    Full Text:
    equally to both synchronous and asynchronous implementations, it is only the underlying circuit

  • Design of an asynchronous third-order finite impulse response filter

    Creator:
    Oren, Joel A.
    Abstract:
    With the increased demand for complex digital signal processing systems, real-time signal processing requires higher throughput systems. In the past, the throughput has been increased by increasing the clock rates, but synchronization can become increasingly more difficult. Recently there has been renewed interest in designing asynchronous digital systems. In an...
    Resource Type:
    Masters Thesis
    Full Text:
    circuit techniques. These asynchronous design techniques are used to test whether a practical signal

  • Micro data flow processor design

    Creator:
    Chang, Chih-ming
    Abstract:
    Computer has evolved rapidly during the past several decades in terms of its implementation technology; it's architecture, however, has not changed dramatically since the von Neumann computer(control flow) model emerged in the 1940s. One main reason is that the performance for this kind of computers was able to satisfy the...
    Resource Type:
    Masters Thesis
    Full Text:
    use the selftimed(asynchronous) implementation methodology. It features advan- tages such as free of

  • Efficient arithmetic using self-timing

    Creator:
    Ramachandran, Ravichandran
    Abstract:
    The recent advances in VLSI technology have facilitated feature shrinking and hence a rapid increase in the levels of integration at the chip level. This increase in the level of integration has brought along with it a host of other constraints, the most crucial being timing management and increased power...
    Resource Type:
    Masters Thesis
    Full Text:
    of complex digital systems. Systems designed using this self-timed or asynchronous protocol, work on

  • Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

    Creator:
    Hanken, Christopher
    Abstract:
    Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
    Resource Type:
    Masters Thesis
    Full Text:
    : Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic

  • Comparison and impact of substrate noise due to clocked and clockless circuitry

    Creator:
    Le, Jim K.
    Abstract:
    Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
    Resource Type:
    Masters Thesis
    Full Text:
    larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor

  • A numerical study of the thermal performance for surface mounted and through-hole mounted integrated circuits

    Creator:
    Wang, Jyi-Ren
    Resource Type:
    Masters Thesis
    Full Text:
    completed, the results were presented for convenient evaluation. The postprocessing capabilities of the

  • Characterization of a digital phase locked loop and a stochastic time to digital converter

    Creator:
    Geissenhainer, Erik D.
    Abstract:
    A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...
    Resource Type:
    Masters Thesis
    Full Text:
    range of input conditions. Evaluation of the DPLL’s digitally controlled analog oscillator (DCAO