This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively.
The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
Intuitively, it seems as though natural language processing tasks might benefit from explicit representations of the syntactic and semantic properties of text. Ontonotes is a dataset which attempts to annotate texts, to represent as much as possible of the meaning of the text explicitly within the annotation. Many tools exist...
Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently, SAR ADCs are also penetrating into the applications which have been earlier dominated by delta-sigma ADCs and pipeline ADCs. However, the resolution of SAR ADCs...
IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This...
In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been...
Continuous-time ΔΣ modulators are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requirements while maintaining good power efficiency, multi-bit feedback is typically used. This approach provides benefits such as lower OSR, relaxed loop filter requirements, and reduced jitter sensitivity....
As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links...
As more features are being integrated into mobile platforms, the demand for
long battery life during standby mode has been increasing. Light load efficiency
becomes one of essential features in today's DC-DC converter. The most effective
method to improve light load efficiency is to operate the DC-DC converter under
pulse-frequency-modulation...
This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise.
In the calibration mode, the incremental ADC...
Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....