This thesis describes the analysis and comparison of Folded Source-Coupled
Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential
split-level logic gates. The advantages of FSCL are low switching noise and
high operating speed. The effect of voltage and device scaling on these topologies is
evaluated in terms...
An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is presented. It is shown that the ESD structures degrade LNA performance particularly for higher frequency applications. Two LNAs, one with ESD protection and one without,...
A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as
an asynchronous storage element in micropipelines or a part of the synchronizer. It is
capable of double-edge triggering which latches data at both the rising and the trailing
edges. It is also free of the...
We present a new circuit design for adaptive offset cancellation in a fully differential 2.4 GHz CMOS direct conversion mixer. Our circuit structure is a modification of a Gilbert cell mixer in which offsets are cancelled by injecting cancellation currents into the legs of the mixer by dynamically varying the...
Previous work at Stanford University has demonstrated that inductance in the
substrate connection is the principal problem underlying the coupling of digital
switching noise into analog circuits. The low impedance substrate can be treated
as a single node over a local area. Switching in the digital circuits produces
current transients...
A fully integrated CMOS latched comparator is presented for use as a wake-up circuit that is attached to an RF energy harvester in a battery free wireless sensor network. The system consumes less than 36nA static current at 20°C and dissipates 2pJ of energy per conversion. The comparator comprises of...
With the advancement of technology, submicron CMOSonly process is available now for
Application Specific Integrated Circuits (ASICs). The high integration leads to the need for
high pin counts. However voltage supply and ground bounce due to many output drivers
switching at the same time is becoming a major problem. In...
With increasing interest in current-mode analogue processing due to its high
performance properties such as speed, bandwidth and accuracy compared to voltage-mode
processing, new current-mode alternatives to various conventional circuit designs are
appearing. In this report, a novel circuit design to construct a fully-differential current-mode
operational amplifier ( OP-AMP )...
Advancements in the sophistication and complexity of modern electronic systems are creating a need for highly integrated systems with ever higher operational frequencies. The economical demands of these systems dictate that they be implemented using low cost fabrication technologies, such as digital CMOS. One of the major challenges facing circuit...
A negatively biased substrate has several advantages over a grounded substrate in CMOS
technology. The on-chip generation of this negative substrate bias has made chips easier
to use when only a single supply is preferred. This project demonstrates two types of
charge pump circuits used to generate negative voltages not...