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  • Design methodology for low-jitter phase-locked loops

    Creator:
    Bhagavatheeswaran, Shanthi, S.
    Abstract:
    This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case)...
    Resource Type:
    Masters Thesis
    Full Text:
    Top-down simulation methodology for phase-locked loop.......... 13 2.2 Bottom-up verification of the

  • Design techniques for high-performance digital PLLs and CDRs

    Creator:
    Yin, Wenjing
    Abstract:
    Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as leakage, poor analog transistor behavior, process variability, and low supply voltage is a challenging task. To overcome these drawbacks, digital PLLs (DPLLs) have recently emerged...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3 A low jitter, wide operating range digital phase-locked loop 28 3.1 Introduction