The passive charge compensation (PCC) technique was introduced for switched capacitor (SC) circuit to increase the slew rate and enhance the linearity performance, as PCC techniques are used on the Delta-Sigma modulator (DSM) in ADC circuitry. The PCC technique of the project was applied to the design of a SC...
This thesis work proposes a low-power 12-bit digital-to-analog converter (DAC) designed in a 130nm process. The DAC to be presented is of a segmented design where the architecture is split into pipelined and thermometer coded segments. This allows for high linearity and low distortion while maintaining high speed and low...
Switched capacitor (SC) circuits are the main building blocks in many structures such as filters, data converters, sampling circuits and sampled-data amplifiers. The key challenge is to design such circuits which are the prime components of any IoT system with low power consumption without compromising on the performance. In this...
Filters and data converters are key analog-and-mixed-signal (AMS) building blocks in communication systems, such as software-defined radios and internet-of-things. In this dissertation, novel switched-capacitor filter and analog-to-digital converter (ADC) circuit configurations have been explored which are power efficient and are digital scaling friendly.
First, a novel switched-capacitor low-pass filter architecture...
Analog-to-digital converters are essential components to the portable devices that we are using today. Wireless sensors, body implanted devices, communication devices and so forth require low power ADCs. Therefore achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. In this work power efficient ADCs for...
Continuous-time ΔΣ modulators are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requirements while maintaining good power efficiency, multi-bit feedback is typically used. This approach provides benefits such as lower OSR, relaxed loop filter requirements, and reduced jitter sensitivity....
Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop...
Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....
IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This...
This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively.
The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...