Data converters are ubiquitous building blocks of a signal chain. The rapid increase in
communication and connectivity devices presents new avenues for pushing the state of
the art analog to digital converters. Techniques for improving resolution, bandwidth,
linearity and bit-error rate, while reducing the power, energy and area is the...
An R2R DAC using 3 digital input levels rather than 2 has been
proposed as well as a modified 2-level structure that emulates the 3-level
DAC’s benefits. This 3-level structure provides and power reductions of
79% and linearity improvements due to matching of a factor of 2 over
the 2-level...
The internet-of-things is a growing market segment which is based on an arrayof portable communication devices with high power efficiency. Advanced semiconductortechnology can easily improve their digital performance, but the samecannot be said for the analog blocks which are vital to their operation. Highperformance analog circuits continue to use conventional...
An analysis of the statistics of multi-stage (pipeline, SAR and algorithmic) ADCs with redundancy is performed and the ability to achieve an extra 6dB of resolution in ADCs with half-bit redundancy is shown due to probability density function (PDF) residue shaping. This paper classifies redundancy techniques to show that only...
In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and...
As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain...
As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog)...
Continuous-time ΔΣ modulators are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requirements while maintaining good power efficiency, multi-bit feedback is typically used. This approach provides benefits such as lower OSR, relaxed loop filter requirements, and reduced jitter sensitivity....
Incremental ADCs (IADCs) have many advantages for low-frequency high-accuracy data conversion—they are easy to multiplex between channels, need simpler digital decimation filter, and allow extended counting with a Nyquist-rate ADC. A single-loop incremental ADC was designed and fabricated in 90 nm for a biosensor interface circuit. It incorporates one integrator,...
Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as...