As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links...
This thesis investigates a novel cycloid electric machine that integrates both cycloid gear drive and permanent magnet synchronous machine (PMSM), and proposes to apply the machine in robotic transmission system. Cycloid gear drive is a transmission device that is commonly used to boost up the output torque. It has been...
Transportation systems are facing safety and operational challenges with a cost of billions of dollars annually in lost production time and wasted fuel. Infrastructure expansion, previously held as a panacea to most transportation challenges has lost its appeal due to financial, land-use and environmental constraints. Interest is surging in intelligent...
Current multi-gigahertz ADC performance is
limited by the sampling clock timing jitter. This paper describes
the effects of clock transition time on the spurious-free dynamic
range (SFDR) of a CMOS T/H circuit. A signal-dependent
nonlinearity model is first introduced that provides insight on the
effect of finite clock transition time,...
This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the...
The upper reach of the Hutuo River flows along the Xin-Ding basin and cuts a transverse drainage
through Xizhou Mountain and Taihang Range into the North China Plain. Previous studies showed
that the Xin-Ding basin was occupied by a lake during the Early-Middle Pleistocene. However,
the timing of the paleolake...
A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase...
Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop...