Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells Public Deposited

http://ir.library.oregonstate.edu/concern/articles/9019s4373

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  • It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the piecewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9dB (without calibration) is achieved at 210MSPS from the Verilog synthesized design.
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  • Weaver, S., Hershberg, B., & Moon, U. (2014). Digitally synthesized stochastic flash ADC using only standard digital cells. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(1), 84-91. doi:10.1109/TCSI.2013.2268571
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  • description.provenance : Submitted by Deanne Bruner (deanne.bruner@oregonstate.edu) on 2014-04-02T23:05:45Z No. of bitstreams: 1 MoonUn-KuElectricalEngineeringComputerScienceDigitallySynthesizedStochastic.pdf: 997131 bytes, checksum: e3c70a4950ff416dfed8b88810ec3dbb (MD5)
  • description.provenance : Approved for entry into archive by Deanne Bruner(deanne.bruner@oregonstate.edu) on 2014-04-02T23:06:26Z (GMT) No. of bitstreams: 1 MoonUn-KuElectricalEngineeringComputerScienceDigitallySynthesizedStochastic.pdf: 997131 bytes, checksum: e3c70a4950ff416dfed8b88810ec3dbb (MD5)
  • description.provenance : Made available in DSpace on 2014-04-02T23:06:26Z (GMT). No. of bitstreams: 1 MoonUn-KuElectricalEngineeringComputerScienceDigitallySynthesizedStochastic.pdf: 997131 bytes, checksum: e3c70a4950ff416dfed8b88810ec3dbb (MD5) Previous issue date: 2014-01

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