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Teraohm on-chip resistance realisation using switched capacitor topologies Public Deposited

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Abstract
  • Two large-resistance realisation schemes are proposed using switched-capacitor circuits. The equivalent resistance of the array realisation increases as the third power of the number of capacitor pairs, and that of the ladder realisation increases exponentially. The equivalent resistance for the ladder scheme also grows with the capacitance ratio. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area. Simulation results show that very low pole frequency (~ 9 Hz in the example) can be achieved with practical element values, and with a capacitance spread of only 10 in a three-stage ladder.
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  • Li, W., Wang, T., Cao, J., & Temes, G. (2012). Teraohm on-chip resistance realisation using switched capacitor topologies. Electronics Letters, 48(11), 623-624. doi: 10.1049/el.2012.0767
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  • 48
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  • 11
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  • This work was supported by the NSF Center for the Design of Analog-Digital Integrated Circuits.
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  • description.provenance : Approved for entry into archive by Deanne Bruner(deanne.bruner@oregonstate.edu) on 2013-02-15T21:43:11Z (GMT) No. of bitstreams: 1 LiWeiElectricalEngineeringComputerScienceTeraohmOnChip.pdf: 554511 bytes, checksum: cdeacb3acc039fabaec9cb9e41f5ce1c (MD5)
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