Digital excess loop delay compensation technique with embedded truncator for continuous-time delta–sigma modulators Public Deposited

http://ir.library.oregonstate.edu/concern/articles/p2676x12t

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  • A novel implementation is proposed to relax the specifications of the internal feedback path for a continuous-time delta-sigma modulator. A truncator is embedded into the digital excess loop delay (ELD) compensation path. Thermometer-coded truncation is achieved by re-ordering the reference voltages of the internal quantiser. This requires only a small amount of extra digital circuitry compared to the conventional digital ELD compensation. The digital encoder controlling the digital-to-analogue converter is simple, and it only introduces a small ELD.
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  • He, T., Zhang, Y., & Temes, G. C. (2016). Digital excess loop delay compensation technique with embedded truncator for continuous-time delta–sigma modulators. Electronics Letters, 52(1), 20-21. doi:10.1049/el.2015.1595
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  • description.provenance : Made available in DSpace on 2016-08-02T19:38:19Z (GMT). No. of bitstreams: 1 HeDigitalExcessLoopDelayCompensationTechnique.pdf: 466412 bytes, checksum: 90009f721151eed0ab1260e1f487b801 (MD5) Previous issue date: 2016-01-08
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  • description.provenance : Approved for entry into archive by Deanne Bruner(deanne.bruner@oregonstate.edu) on 2016-08-02T19:38:19Z (GMT) No. of bitstreams: 1 HeDigitalExcessLoopDelayCompensationTechnique.pdf: 466412 bytes, checksum: 90009f721151eed0ab1260e1f487b801 (MD5)

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