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A 0.47-0.66pJ/bit, 4.8-8Gb/s I/O Transceiver in 65nm-CMOS Public Deposited

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Abstract
  • A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100-200mV[subscript ppd] using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. In the transmitter clocking circuitry, per-phase duty-cycle and phase-spacing adjustment is implemented to allow adequate timing margins at low operating voltages. Fabricated in a general purpose 65nm CMOS process, the transceiver achieves 4.8-8Gb/s at 0.47-0.66pJ/b energy efficiency for V[subscript DD]=0.6-0.8V.
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  • Song, Y.H., Bai, R., Hu, K.M., Yang, H.W., Chiang, P.Y. & Palermo, S. (2013). A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O transceiver in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 48(5), 1276-1289. doi:10.1109/JSSC.2013.2249812
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  • This work was supported by the Semiconductor Research Corporation (SRC) under grant 1836.060, the Department of Energy Early Career program, and a gift from the Intel Labs Academic Research Office Wireline Signaling Center.
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  • description.provenance : Submitted by Deanne Bruner (deanne.bruner@oregonstate.edu) on 2013-09-25T22:25:27Z No. of bitstreams: 1 ChiangPatrickElectricalEngineeringComputerScienceIOTransceiverCMOS.pdf: 1049161 bytes, checksum: c1f29935bfadd13fed9559f7e779808a (MD5)
  • description.provenance : Approved for entry into archive by Deanne Bruner(deanne.bruner@oregonstate.edu) on 2013-09-25T22:27:36Z (GMT) No. of bitstreams: 1 ChiangPatrickElectricalEngineeringComputerScienceIOTransceiverCMOS.pdf: 1049161 bytes, checksum: c1f29935bfadd13fed9559f7e779808a (MD5)
  • description.provenance : Made available in DSpace on 2013-09-25T22:27:36Z (GMT). No. of bitstreams: 1 ChiangPatrickElectricalEngineeringComputerScienceIOTransceiverCMOS.pdf: 1049161 bytes, checksum: c1f29935bfadd13fed9559f7e779808a (MD5) Previous issue date: 2013-05

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