Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End Public Deposited

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  • A noise-shaped pipelined ADC is presented in this paper. A minimal complexity ΔΣ modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18μ m CMOS, the ADC achieves 12 ENOB with 64 MHz clock at 6X OSR while using only a 9-bit linear front-end multiplying-DAC (MDAC). The delta-sigma sub-ADCs dissipate 400μ W extra power (out of 13.9mW total power) while significantly enhancing the the overall ADC linearity.
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  • Rajaee, O.; Un-Ku Moon, "Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End," Solid-State Circuits, IEEE Journal of, vol.48, no.2, pp.502,515, Feb. 2013 doi: 10.1109/JSSC.2012.2227605
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  • description.provenance : Submitted by Deanne Bruner (deanne.bruner@oregonstate.edu) on 2013-04-16T00:21:18Z No. of bitstreams: 1 MoonUn-KuElectricalEngineeringComputerScienceHighlyLinearNoise.pdf: 2286731 bytes, checksum: 154dd16170900ef579865795771adf2a (MD5)
  • description.provenance : Made available in DSpace on 2013-04-16T00:22:13Z (GMT). No. of bitstreams: 1 MoonUn-KuElectricalEngineeringComputerScienceHighlyLinearNoise.pdf: 2286731 bytes, checksum: 154dd16170900ef579865795771adf2a (MD5) Previous issue date: 2013-02
  • description.provenance : Approved for entry into archive by Deanne Bruner(deanne.bruner@oregonstate.edu) on 2013-04-16T00:22:13Z (GMT) No. of bitstreams: 1 MoonUn-KuElectricalEngineeringComputerScienceHighlyLinearNoise.pdf: 2286731 bytes, checksum: 154dd16170900ef579865795771adf2a (MD5)

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