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A Ternary R2R DAC design for improved energy efficiency Public Deposited

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Abstract
  • An R2R DAC using 3 digital input levels rather than 2 has been proposed as well as a modified 2-level structure that emulates the 3-level DAC’s benefits. This 3-level structure provides and power reductions of 79% and linearity improvements due to matching of a factor of 2 over the 2-level case. Ideal implementation is also described in terms of the logic needed to code the DAC and the requirements of the additional third reference level.
  • This is an author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220. ©2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
  • Keywords: Digital input levels, R2R circuits, Digital to analog converters (DACs)
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  • Guerber, J.; Venkatram, H.; Gande, M.; Moon, U., "Ternary R2R DAC design for improved energy efficiency," Electronics Letters , vol.49, no.5, pp.329,330, February 28 2013 doi: 10.1049/el.2012.4224
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  • 49
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  • 5
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  • This work was funded in part by the Semiconductor Research Corporation (SRC, GRC Task ID #1836.097) and Texas Instruments.
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