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Sinusoidal Clock Sampling for Multi-Gigahertz ADCs Public Deposited

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This is the author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at:  http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8919.

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  • Sinusoidal Clock Sampling for Multigigahertz ADCs
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  • Current multi-gigahertz ADC performance is limited by the sampling clock timing jitter. This paper describes the effects of clock transition time on the spurious-free dynamic range (SFDR) of a CMOS T/H circuit. A signal-dependent nonlinearity model is first introduced that provides insight on the effect of finite clock transition time, and presents the use of sinusoidal signal as the sampling clock to improve SFDR. Whereas a square-wave clock exhibits a shorter transition time but more jitter susceptibility, sinusoidal clocking provides a longer transition time but a lower jitter spectrum. To verify this concept, an 8GS/s, 4b flash ADC with a sinusoidal clock is designed and experimentally measured, achieving a Figure-of-Merit of 0.86pJ/conv-step based upon ERBW (Effective Resolution Bandwidth), and 0.2pJ/conv-step based upon sampling rate.
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  • Rui Bai; Jingguang Wang; Lingli Xia; Feng Zhang; Zongren Yang; Weiwu Hu; Chiang, P.; , "Sinusoidal Clock Sampling for Multigigahertz ADCs," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.58, no.12, pp.2808-2815, Dec. 2011 doi: 10.1109/TCSI.2011.2157742
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  • This work is supported by NSF, the National Natural Science Foundation of China under grant no.60736012 and 60921002.
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  • description.provenance : Made available in DSpace on 2013-01-03T00:58:05Z (GMT). No. of bitstreams: 1 ChiangPatrickElectricalEngineeringComputerScienceSinusoidalClockSampling.pdf: 1934106 bytes, checksum: 5c9432772d1fde10b226234a04263c89 (MD5) Previous issue date: 2011-12
  • description.provenance : Approved for entry into archive by Deanne Bruner(deanne.bruner@oregonstate.edu) on 2013-01-03T00:58:05Z (GMT) No. of bitstreams: 1 ChiangPatrickElectricalEngineeringComputerScienceSinusoidalClockSampling.pdf: 1934106 bytes, checksum: 5c9432772d1fde10b226234a04263c89 (MD5)
  • description.provenance : Submitted by Deanne Bruner (deanne.bruner@oregonstate.edu) on 2013-01-03T00:56:32Z No. of bitstreams: 1 ChiangPatrickElectricalEngineeringComputerScienceSinusoidalClockSampling.pdf: 1934106 bytes, checksum: 5c9432772d1fde10b226234a04263c89 (MD5)

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