Flex 1 user's manual Public Deposited

http://ir.library.oregonstate.edu/concern/defaults/xw42n912b

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  • FLEX1 is a general model processor, patterned after Klir's General Sequential System Paradigm (Figure 1). Specifically, the processor is a discrete time flux oriented realization of the general paradigm and can process non-linear, non-stationary, environmentally controlled state variable system models with explicit memory. The current version is restricted to not more than 63 state variables, 40 input variables, 200 memory variables, and 50 output variables. There are also restrictions on the number of functions identified, and other restrictions, which will be elaborated in the appropriate part of this writeup. The system is implemented in the Oregon State University OS-3 operating system, is specific for the CDC 3300 computer, and may be operated only from a teletype. Output may be monitored at the teletype, line printed and dump filed. Satellite programs have been written for plotting and listing from the dump file. FLEX1 is designed to be expanded in two directions. First will be further elaboration as a single level model processor concentrating all capacity into this single level. Second will be elaboration into a multi-level, hierarchical model processor (REFLEX), capable of mixed resolution. The two capacities are being incorporated into a single processor, FLEXZ, which is in the final stage of development at this printing, and will be operative in late 1973.
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