Graduate Project


Three-Dimensional Network-on-Chip Architectures for Cycle Accurate Full-System Simulator Public Deposited

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  • High Performance Computing can find ubiquitous applications in the industry. HPC-applications are specifically designed to take advantage of the parallel nature of the computing systems which is often enabled by Multi-core/Many-core architectures. With this advent of Multi-processors in the mainstream systems, inter-core communication has been one of the major challenges as it affects the full-system performance, thus making Network-on-Chip, which connects different components, an integral part of chip design. Since the On-Chip Network topology determines the physical layout and how connections are laid-out between the nodes, it has a profound impact on overall network-performance. Recently, there has been a surge in the number of articles proposing 3D mesh topologies for Systems research. This Master’s report reflects the motivation and efforts needed to implement 3D topology models (3D mesh and 3D-stacked mesh) in the Gem5 Simulator to serve as a foundation in simulating all future 3D NoC related researches. Gem5 is a Cycle-accurate full-system simulator highly used in Computer Architecture research. This project solely focuses on enabling 3D mesh Network simulations on GARNET which is a cycle-accurate interconnection network model inside Gem5 simulator and primarily consists of 2D network designs only. The report also discusses a very sound approach of determining the position of TSV links (vertical links) in the 3D stacked mesh NoC design.
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