Single fault detection in combinational logic circuits

Graduate Project

Público Deposited

Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_projects/tb09jd68n

Descriptions

Attribute Name	Values
Creator	Medhekar, Ranjana A.
Abstract	The material in this paper is divided into the following four chapters for convenience. Chapter 1 explains, how the idea of fault testing changed from testing the machine instructions to testing the hardware in logic circuits. Chapters 2, 3 and 4 present the different approaches considered, namely: 1. Path sensitizing and D-Algorithm method. 2. Tabular method. 3. Boolean difference method.
Resource Type	Capstone Project
Fecha de Emisión	1972-09-08
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Computer Science
Degree Grantor	Oregon State University
Commencement Year	1972
Advisor	Short, Robert A.
Academic Affiliation	Electrical and Electronics Engineering
Declaración de derechos	In Copyright
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
File Format	pdf

Miniatura	Título	Fecha de subida	Visibilidad	Acciones
	Medhekar_Ranjana_A_1972_09.pdf	2023-02-02	Público	Descargar