A multi-bit hybrid DSM over full-scale range without feedback DEM Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/00000194g

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  • Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications due to the opamp settling requirement. Alternatively, a continuous-time (CT) ∆ΣM can be used to decrease power consumption but has its own disadvantages such as clock jitter sensitivity, RC time constant variation, and excess loop delay. The wideband modulators are often implemented as single-loop high-order modulators in a deep submicron process. The high-order modulator typically has a quantizer overloading problem as the input signal approaches to a full-scale range. A pole-optimization method can be used to extend the linear input range but it inevitably decreases signal to quantization noise ratio. This causes power penalty since it limits the maximum input power available. Another challenge is linearizing a nonlinear multi-bit Digital-to-Analog Converter (DAC). On one hand, the DAC can be linearized by element sizing, sorting, and calibration but these increase silicon area and power consumption. On the other hand, a Dynamic Element Matching algorithm (DEM) linearizes the DAC by averaging and shaping the mismatches with minimal design overhead. However, the DEM causes additional delay inside the feedback path. This can make the modulator unstable. In this thesis, a multi-bit 3rd-order hybrid ∆ΣM with over full-scale range and no DEM in the critical feedback path is presented. Removing the DEM in the critical path enables the modulator to minimize latency in the feedback path. A digital feedforward structure allows processing the input signal over the full-scale reference voltage. Combined benefits of the CT/DT implementation help to reduce power consumption and to mitigate the loop delay. Measurement results from a prototype demonstrate the effectiveness of the proposed ideas.
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