## Descriptions

Attribute NameValues
Creator
Abstract
• In recent years, SAR ADCs have been shown to acheive faster conversion times and improved power efficiencies due to their simple building blocks that are digital in nature and scale favorably with technology. High resolution ADCs with stringent noise requirement has led to the adoption of hybrid ADC architectures such as the two-step SAR. The two-step SAR ADC, also known as pipelined SAR ADC, combine the concepts of SAR and Pipeline ADC architecture where a residue amplifier provides a critical amplification step. An amplifier architecture well suited for residue amplification known as Ring Amplifier (RAMP) has enabled power efficient two-step SAR ADCs. However, RAMP based ADCs with greater than 14 bits of resolution has not been attempted in previous literature. In this work, the design and measurement of a high-resolution two-step SAR ADC utilizing an enhanced RAMP is demonstrated. Additional circuit techniques are introduced that contribute to the energy-efficiency of the ADC. The ADC implemented in 0.18$\mu$m technology achieves a DR of 95dB and a Schreier FOM better than 180dB at both 2MS/s and 15MS/s.
Resource Type
Date Issued
Degree Level
Degree Name
Degree Field
Degree Grantor
Commencement Year
Committee Member
Rights Statement
Publisher
Peer Reviewed
Language
Embargo reason
• Ongoing Research
Embargo date range
• 2019-05-17 to 2020-06-18

## Relationships

Parents:

This work has no parents.

In Collection: