Graduate Thesis Or Dissertation

 

Design of a 14-bit continuous-time Delta-Sigma A/D modulator with 2.5MHz signal bandwidth Public Deposited

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/02870z41z

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  • In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications. So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s). This dissertation presents the realization of a continuous-time (CT) Δ-Σ A/D modulator providing 80.5dB SNDR and 85dB DR with 5MS/s output data rate in a 2.5V 0.25µm CMOS process. The modulator has a single-stage dual-loop architecture allowing large quantizer delay. A 17-level quantizer is used to increase resolution and non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome time-constant variation. On-chip self-calibration is implemented to suppress DAC nonlinearity. Combining techniques to address various design challenges, the modulator consumes 50mW with 60MHz sampling rate.
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  • description.provenance : Submitted by Zhimin Li (liz@onid.orst.edu) on 2006-03-02T23:52:01Z No. of bitstreams: 1 zhimin_thesis.pdf: 1493844 bytes, checksum: 380117de2c9ae0589d8117e86e2b7eb1 (MD5)
  • description.provenance : Made available in DSpace on 2006-03-06T15:26:02Z (GMT). No. of bitstreams: 1 zhimin_thesis.pdf: 1493844 bytes, checksum: 380117de2c9ae0589d8117e86e2b7eb1 (MD5)
  • description.provenance : Approved for entry into archive by Julie Kurtz(julie.kurtz@oregonstate.edu) on 2006-03-02T23:58:44Z (GMT) No. of bitstreams: 1 zhimin_thesis.pdf: 1493844 bytes, checksum: 380117de2c9ae0589d8117e86e2b7eb1 (MD5)

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