Leakage power minimization by considering self-bias transistor and pin reordering technique Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/05741v02h

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  • Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold current. Minimizing leakage is gaining increasing importance along with other critical design aspects primarily due to the growing demand for portable battery-operated electronic devices such as laptops and cell phones. Several techniques have been proposed in the past to reduce sub-threshold leakage in circuits. However, most of these are focused on reducing standby leakage current, when the circuit is not operational with little or no emphasis on active leakage reduction. This work presents a novel circuit implementation using a self-bias transistor (SBT) and an efficient transistor placement technique in stacks to minimize sub-threshold leakage current in digital CMOS circuits, both in active and standby modes. The implementation is tested using logic gates in different CMOS process technology using Taiwan Semiconductor Manufacturing Company (TSMC) models and Berkeley's predictive technology models for O.13 [mu]m, lOOnm and 7Onm devices. The simulations were done using HSPICE circuit simulator with accurate models for transistor stacking and parasitics. The results obtained from the simulation of benchmark circuits indicate up to 40% reduction in leakage power in circuits of current process technology and up to 60% reduction in future technologies where leakage in circuits will be significantly higher due to short channel effects.
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