Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/05741x33x

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  • The new CMOS folded source-coupled logic (FSCL) technique intended for mixed-mode integrated circuits has been designed. It has advantages over conventional CMOS circuit in terms of reduced current spike, circuit delay, logic flexibility, and layout density. A simple CPU implemented in 2 μm CMOS technology with a 5.0 volt supply has resulted in 500 μA current spike and operation frequency of 60 MHz.
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