Graduate Thesis Or Dissertation

Power Efficient Architectures for Medium-high Resolution Analog-to-Digital Converters

Public Deposited

Downloadable Content

Download PDF


Attribute NameValues
  • Analog-to-digital converters are essential components to the portable devices that we are using today. Wireless sensors, body implanted devices, communication devices and so forth require low power ADCs. Therefore achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. In this work power efficient ADCs for medium-high resolution is presented. In this dissertation first an ultra-low power successive approximation register SAR ADC is presented. The ADC is an 11-bit single-ended, low power, area efficient one with small loading effect, targeted for biomedical applications. The design features an energy-efficient switching technique to cover an input range twice the reference voltage. The ADC’s loading effect to previous stage is reduced by using single-ended structure and eliminating the largest capacitor (MSB capacitor) in the switching network. All building blocks were designed in subthreshold for power efficiency, with asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 µm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/-0.37 LSB and the INL +0.94/-0.89 LSB. The total power consumption was 250 nW from a 0.75V supply voltage. This gives a Walden FoM of 28.8 fJ/Conv-step. In addition, a noise-coupled VCO-based quantizer is presented. By applying the noise-coupling technique a second order noise-shaped quantizer is achieved, which gets one order from VCO-quantizer and another order from noise-coupling technique. This quantizer is employed as the second stage in a 2-2 MASH delta-sigma modulator with 4rd order noise-shaping. Thus the input signal range of the VCO is the quantization error of the first stage and it is in the linear range of the VCO. OPAMP sharing technique is used between the first and second stage to save power. Proposed architecture was designed and implemented in 0.18 µm CMOS 2P6M process at sampling frequency of 160 MHz with 8 MHz bandwidth. The achieved peak SNDR is 80.54 dB and SFDR is 94 dB. Finally a 3rd order passive delta-sigma modulator employing a VCO-based quantizer is presented. A conventional passive delta-sigma modulator and proposed passive delta-sigma modulator has been designed and simulated for comparison. The results show power efficiency for the proposed structure.
Resource Type
Date Issued
Degree Level
Degree Name
Degree Field
Degree Grantor
Commencement Year
Committee Member
Academic Affiliation
Rights Statement
Embargo reason
  • Ongoing Research
Embargo date range
  • 2018-02-19 to 2018-07-11



This work has no parents.

In Collection: