Graduate Thesis Or Dissertation
 

Satellite multiplication package for a small digital computer

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  • This thesis is concerned with the design of an external multiplication package which can be utilized as an I/O device with a PDP-8/L computer. The multiplier and multiplicand are assumed to be 12 bit integers. The 24 bit product can be transferred back to the accumulator of computer 12 bits at a time. The control pulses for the operation are supplied by the computer through I/O transfer instructions. The multiplication package was constructed on three printed-circuit cards, using only standard TTL IC chips. No other components were needed. It is simple, inexpensive and much faster than the method of repeated addition which must ordinarily be used in the PDP-8. This paper also shows a division algorithm using the multiplier and trial-and-error. This method of division is faster than repeated subtraction.
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  • File scanned at 300 ppi (Monochrome) using Capture Perfect 3.0.82 on a Canon DR-9080C in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
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