Fine-grain parallelism on sequential processors Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/0p096948p

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  • There seems to be a consensus that future Massively Parallel Architectures will consist of a number nodes, or processors, interconnected by high-speed network. Using a von Neumann style of processing within the node of a multiprocessor system has its performance limited by the constraints imposed by the control-flow execution model. Although the conventional control-flow model offers high performance on sequential execution which exhibits good locality, switching between threads and synchronization among threads causes substantial overhead. On the other hand, dataflow architectures support rapid context switching and efficient synchronization but require extensive hardware and do not use high-speed registers. There have been a number of architectures proposed to combine the instruction-level context switching capability with sequential scheduling. One such architecture is Threaded Abstract Machine (TAM), which supports fine-grain interleaving of multiple threads by an appropriate compilation strategy rather than through elaborate hardware. Experiments on TAM have already shown that it is possible to implement the dataflow execution model on conventional architectures and obtain reasonable performance. These studies also show a basic mismatch between the requirements for fine-grain parallelism and the underlying architecture and considerable improvement is possible through hardware support. This thesis presents two design modifications to efficiently support fine-grain parallelism. First, a modification to the instruction set architecture is proposed to reduce the cost involved in scheduling and synchronization. The hardware modifications are kept to a minimum so as to not disturb the functionality of a conventional RISC processor. Second, a separate coprocessor is utilized to handle messages. Atomicity and message handling are handled efficiently, without compromising per-processor performance and system integrity. Clock cycles per TAM instruction is used as a measure to study the effectiveness of these changes.
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  • File scanned at 300 ppi (Monochrome, 256 Grayscale) using Capture Perfect 3.0 on a Canon DR-9050C in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
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  • description.provenance : Submitted by Kirsten Clark (kcscannerosu@gmail.com) on 2012-11-19T20:15:23Z No. of bitstreams: 1 KotikalapoodiSridharV1995.pdf: 3007269 bytes, checksum: 7f5c207f7ef6d250a5080df0cb6a4062 (MD5)
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-11-21T18:31:19Z (GMT) No. of bitstreams: 1 KotikalapoodiSridharV1995.pdf: 3007269 bytes, checksum: 7f5c207f7ef6d250a5080df0cb6a4062 (MD5)
  • description.provenance : Made available in DSpace on 2012-11-26T17:59:06Z (GMT). No. of bitstreams: 1 KotikalapoodiSridharV1995.pdf: 3007269 bytes, checksum: 7f5c207f7ef6d250a5080df0cb6a4062 (MD5) Previous issue date: 1994-09-07
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-11-26T17:59:06Z (GMT) No. of bitstreams: 1 KotikalapoodiSridharV1995.pdf: 3007269 bytes, checksum: 7f5c207f7ef6d250a5080df0cb6a4062 (MD5)

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