Model and design of cmos phase-locked loop Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/1z40kx083

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  • This thesis will examine the model and design technique of a self-contained analog CMOS Phase-Locked Loop. This system has an adaptable filter and demodulator for an oscillating frequency of up to 1000 KHz and it is programmable by means of an external resistor and capacitor. The first topic to be presented will be the nonlinear feedback system concept and terminology, then the mathematical analysis for the phase comparator, low-pass filter, voltage-controlled oscillator and capture and lock range is developed. Finally, the circuit parameters, description, simulation and layout will be presented.
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  • description.provenance : Made available in DSpace on 2013-06-04T19:09:20Z (GMT). No. of bitstreams: 1 ShumDanielK1990.pdf: 2903516 bytes, checksum: f00162c95b935ba2981e91841d74697b (MD5) Previous issue date: 1989-06-29
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-05-10T16:06:16Z (GMT) No. of bitstreams: 1 ShumDanielK1990.pdf: 2903516 bytes, checksum: f00162c95b935ba2981e91841d74697b (MD5)

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