Graduate Thesis Or Dissertation

 

High-speed CMOS dual-modulus presalers for frequency synthesis Public Deposited

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  • Phase-locked loop (PLL) frequency synthesizers lie at the heart of most radio transceivers. An important objective of the electronics and communications industry is to design high-speed building blocks which dissipate the lowest possible power, and to ac- complish this with the cheapest technology. The dual-modulus prescaler is one of the key components of a PLL-based frequency synthesizer, operating at gigahertz frequencies. While several previous implementations have utilized the advantages of a high-speed, but expensive technology, the growing trend towards integrating the frequency synthesizer on a single chip is the motivation behind silicon-CMOS implementations. This thesis addresses the issues in the design of CMOS prescalers for frequency synthesis. A design methodology is obtained to improve the performance of integrated prescalers using the current mode style of operation. An 8/9 dual-modulus prescaler prototype has been designed to obtain speeds of the order of 2.5-3 GHz while minimizing the power con- sumed to 2.5 mW. The circuit was implemented in a 0.25µm National BiCMOS process. Measurement results of the prototype have also been obtained.
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