Delta-sigma analog-to-digital converters traditionally have been used for low speed, high
resolution applications such as measurements, sensors, voice and audio systems.
Through continued device scaling in CMOS technology and architectural and circuit
level design innovations, they have even become popular for wideband, high
dynamic range applications such as wired and wireless communication systems.
Therefore, power efficient wideband low power delta-sigma data converters that bridges
analog and digital have become mandatory for popular mobile applications today.
In this dissertation, two architectural innovations and a development and
realization of a state-of-the-art delta-sigma analog to digital converter with effective design
techniques in both architectural and circuit levels are presented. The first one is
timing-relaxed double noise coupling which effectively provides 2nd order noise
shaping in the noise transfer function and overcomes stringent timing requirement
for quantization and DEM. The second one presented is a noise shaping SAR
quantizer, which provides one order of noise shaping in the noise transfer function.
It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion
delta-sigma modulator which is suitable for adopting SAR quantizer.
Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for
WLAN applications is presented. It uses a noise folding free double sampling
technique and an improved low-distortion architecture with an embedded-adder
integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18μm
CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz
bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27
pJ/conv-step. The measurement results indicate that the proposed design ideas are
effective and useful for wideband, low power delta-sigma analog-to-digital converters with
low oversampling ratio.