Low-power successive approximation analog to digital converter with digital calibration Public Deposited



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  • IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
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Last modified: 10/27/2017

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