Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/3b591c96t

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  • Minimizing the number of product terms in a PLA implementation is a large step towards saving area on a VLSI chip using PLA logic. Due to the large amounts of computer time necessary to achieve this minimization, a number of heuristic approaches have been developed to provide near-optimal solutions in a smaller amount of time. One such approach is the Pronto Algorithm. Through the expansion of selected product terms, Pronto produces larger cubes covering a number of the remaining product terms, which then become redundant. A significant amount of time is required to determine the validity of a given product term expansion. The sharp operation currently used for this test is slow compared to the intersection operation. By replacing a sharp with an intersection, significant time savings are achieved. One way to do this is to intersect the expanded cube with the complement of the original function. Tests show that this produces the same result in less time. The tests were designed to decide whether or not the time savings gained by using this technique would justify the overhead in run time necessary to perform a one-time generation of the complement of the PLA function at the beginning of the program. Test results show that the time used to generate the complement of the PLA function was more than offset by the time savings gained later. More importantly, the saving in time grows as the size of the PLA grows.
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