Conventional Delta-Sigma analog-to-digital converters (ADCs) utilize operational transconductance amplifiers (OTAs) in their loop filter implementation followed by multi-bit voltage domain quantizers. As CMOS integrated circuit technology scales to smaller geometries, the minimum transistor length and the intrinsic gain of the transistors decrease. Moreover, with process scaling the voltage headroom decreases as well. Therefore, designing OTAs in advanced CMOS processes is becoming increasingly difficult. Additionally, multibit quantizers are becoming more difficult to design due to the decreased voltage headroom and the challenges of low offset and noise requirements.
In this thesis, alternative digital solutions are introduced to replace traditional analog blocks. In the proposed solutions, compressed voltage-domain processing is shifted to the time-domain which benefits from process scaling as the transistors scale down in size and become faster.
First, a novel highly linear VCO-based 1-1 multi stage noise shaping (MASH) delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. A prototype was fabricated in a 65nm CMOS process and achieves 79.7 dB SNDR for a 2MHz signal bandwidth. Second, a novel time-domain phase quantization noise extraction for a VCO-based quantizer is introduced. This technique is independent of the OSR and the input signal amplitude of the VCO-based quantizer making it attractive for higher bandwidth applications. Using this technique, a novel 0-1-1 MASH ADC is presented. The first stage is implemented using a 4-bit SAR ADC. The second and the third stages use a VCO-based quantizer (VCOQ). Behavioral simulation results conrm second-order noise shaping with a 75dB SNDR for an OSR of 20.