Characterization of a digital phase locked loop and a stochastic time to digital converter Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/41687n42k

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  • A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited range of input conditions. Evaluation of the DPLL's digitally controlled analog oscillator (DCAO) revealed that transistor mismatch resulted in a non-ideal tuning curve. Simulations and measurements of the DCAO phase noise showed good correlation. The STDC circuit was characterized for several test chips. Measurement results show good matching between the chips for the same input conditions. The ability to achieve higher resolution than standard time-to-digital converters is demonstrated through simulations and measurements.
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  • description.provenance : Approved for entry into archive by Julie Kurtz(julie.kurtz@oregonstate.edu) on 2006-08-01T16:30:35Z (GMT) No. of bitstreams: 1 Geissenhainer_2006.pdf: 4933629 bytes, checksum: 945f512c704075274507b43b28ad949d (MD5)
  • description.provenance : Submitted by Erik Geissenhainer (geissene@onid.orst.edu) on 2006-07-31T21:26:42Z No. of bitstreams: 1 Geissenhainer_2006.pdf: 4933629 bytes, checksum: 945f512c704075274507b43b28ad949d (MD5)
  • description.provenance : Made available in DSpace on 2006-08-03T14:42:54Z (GMT). No. of bitstreams: 1 Geissenhainer_2006.pdf: 4933629 bytes, checksum: 945f512c704075274507b43b28ad949d (MD5)

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