Graduate Thesis Or Dissertation
 

Compensation method of the excess loop delay in continuous-time delta-sigma ADCs based on model matching approach

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  • Continues-Time (CT) Delta-Sigma (ΔΣ) Analog-to-Digital Converters (ADCs) have one important constrain, namely the excess loop delay. Most previous excess lop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distribution random variable. In order to improve system performance with the same loop filter, a new compensation algorithm for the excess loop delay of CT ΔΣ ADCs based on the model matching method is presented in this thesis. By the new equivalence found by Cherry and Snelgrove, model matching algorithm can compensate for the adverse effects of the excess loop delay over a range of values efficiently. Compared to previous compensation methods, the model matching algorithm is more practical because the value of the excess loop delay varies randomly every clock period. It is proved through simulation that our mean value based algorithm can improve the SQNR performance of CT ΔΣ ADCs for the most probable values of the excess loop delay.
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