Graduate Thesis Or Dissertation

A resource-constrained scheduling scheme that considers resources operating at multiple voltages and register assignment

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  • Power and timing requirements are becoming more and more stringent as applications move from less mobile devices to more mobile ones. As such, it is important to optimize these applications as much as possible in order to provide the best solution that is low power and low latency. Although there are many different techniques to achieve a low power, low latency solution, this thesis focuses specifically on low power scheduling at the behavioral level where resource-constrained scheduling is the technique of choice since it directly considers the resource limitations of mobile devices. Conventional resource-constrained scheduling schemes are concerned with minimizing the latency or improving the speed of an algorithm--represented by a data flow graph (DFG)--given a limitation on resources. However, these conventional resource-constrained scheduling schemes are no longer applicable since power has grown to be a major issue, especially in mobile devices. Hence, the conventional resource-constrained scheduling schemes gave way to current resource-constrained scheduling schemes that utilize multiple voltages, which work to find a balance between speed and power. These current multiple voltage schemes use various techniques to balance and meet the speed and power requirements. But while they do a good job of meeting these requirements, they fail to address a new issue that is beginning to surface the number of memory registers needed. Therefore, to address this new arising issue, this paper presents a novel resource-constrained scheduling scheme that balances the speed, power, and register requirements. This algorithm is compared to both a conventional resource-constrained scheduling scheme and a current resource-constrained scheduling scheme with multiple voltages to show that it performs better in finding a scheduling solution. Benchmark results show that, on average, our algorithm has a better power savings while keeping the maximum number of registers needed and the latency low compared to conventional resource-constrained scheduling schemes and current resource-constrained scheduling schemes utilizing just multiple voltages.
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