|Abstract or Summary
- Better performance has been one of the main motivations behind the recent resurgence
of interest in asynchronous circuits (no matter whether this is always true or not).
We are particularly interested in the performance of pipelines since they are used extensively
in current digital systems. There exists an algorithm that can find the exact upper
and lower bounds on the separation time of events in a certain class of process graphs.
However, some transformations and complex mathematical analyses, such as graph decomposition
for infinite unfolded process graphs must be employed in order to reach
exact bounds. This algorithm may be a good candidate for the application of CAD tool
development and circuit synthesis, but it tends to block designers from visualizing what
factors really affect the performance of asynchronous circuits.
In this thesis, a simple approach is adopted to approximate the performance
bounds. Since our method is a symbolic approach instead of a numerical approach, it
allows designers to analyze the circuit performance while providing design guidelines
and approaches at the same time. Our approach has two steps. First, several basic
modules are chosen, including FIFO, Fork, Join, Toggle/XOR, Arbiter/Call and Select/XOR. The individual output loop delay, equivalent input delay and equivalent output
delay are derived based on the Equal loopdelay theorem. The result is a set of difference
equations. The performance approximation can be obtained with simple mathematical
operations on the difference equations, given the bounds of stagedelays. That is,
the performance bounds of output loop delay, equivalent input delay and equivalent output
delay can be represented as the bounds of stagedelays. Second, for a larger system
consisting of those basic modules, its performance bounds can be derived directly from
the bounds of output loop delay, equivalent input delay and equivalent output delay of
those basic modules which have been obtained already. This approach allows a fast and
easy calculation of performance bounds, avoiding the need to rederive the difference
equations for the whole system. Both modular design and performance approximation
are possible with our approach.