Graduate Thesis Or Dissertation

A Wide Modulation Range and PVT-Tolerant Spread-Spectrum Modulation Clock Generator

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  • This dissertation presents a phase domain in-loop-bandwidth spread-spectrum clock generation technique. In this proposed technique, a charge-based discrete-time loop filter is proposed to enable the phase domain in-loop-bandwidth spread-spectrum modulation without a delta-sigma modulator or time-to-digital converter. The in-loop-bandwidth modulation technique maximizes the loop bandwidth to improve phase noise suppression in a ring-based voltage-controlled oscillator. The phase domain modulation is established to eliminate a delta-sigma modulator that presents an undesirable power and noise trade-off. An analog-domain phase modulation in this proposed modulation technique eliminates a time-to-digital converter that results in inevitable quantization noise. The proposed technique delivers a wide spread-spectrum modulation range with significantly relaxed PVT sensitivity. Since the proposed discrete time loop filter acquires and filters signals in the charge domain, this loop filter supports good linearity for a wide modulation range. PVT variations in the loop filter and the voltage-controlled oscillator are attenuated by the loop gain. The nonlinearity of the voltage-controlled oscillator gain (K[subscript VCO]) and loop filter is also attenuated due to the loop gain. In addition, a correlated double sampling technique is leveraged to minimize 1/f noise and DC offset of the proposed discrete-time loop filter. This dissertation discusses design trade-offs: between reference frequency and spread-spectrum modulation range, and between the spread-spectrum modulation range and jitter performance. From time and spectral measurements for various reference frequencies, a higher reference frequency results in better jitter performances, but also a narrow spread-spectrum modulation range. Time domain jitter measurements are compared to spectral domain jitter calculations to observe design intuitions. This wide modulation range and PVT-tolerant spread-spectrum modulation technique is implemented in a 0.18µm CMOS, while consuming 9.93mW with a 1.8V power supply. The proposed charge-based discrete time loop filter consumes less than 10% of the total power, and the spread-spectrum modulation component requires less than 5% of the total power. This wide range spread-spectrum clock generation technique achieves 0.8% and 3.2% spread-spectrum modulation range with 22.76dB and 26.51dB spread-spectrum attenuation for 2MHz and 8MHz reference frequencies, respectively. The measured absolute jitter is 62.72ps[subscript rms] and 18.72ps[subscript rms] for 2MHz and 8MHz reference frequencies, respectively. The measured period jitter is 961.2fs[subscript rms] and 988.1fs[subscript rms] for 2MHz and 8MHz reference frequencies, respectively. Finally, a 142% change in KVCO results in less than 298ppm modulation range error, which confirms the PVT-tolerant modulation.
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  • 2017-08-16 to 2018-02-27



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