The architecture of a multimedia multiprocessor Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/5x21tj02c

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  • The multimedia capabilities of computers have recently become the focus of computer developers due to the increasing demand for advanced computer graphics and new media capabilities, such as video conferencing, 3-D visualization, and animation. To support these multimedia capabilities, specialized graphics hardware, such as MPEG encoding/decoding card, 3-D graphics card, video card, and sound card, are widely used today, but the price of a separate board is expensive. Therefore, the processor must be redesigned from the ground up to handle new media applications. Although these multimedia functions are typically consist of simple operations, their sheer volume of computation creates a flood of data. To support such large volumes of multimedia data computation, Sun Microsystems implemented a specialized instruction set, called VIS[Trademark] (Visual Instruction Set), which is Single Instruction Multiple Data (SIMD) style of instruction. The basic concept behind VIS is to break the pipeline of the Floating Point Unit (FPU) into two or four parallel pipelines to perform four or eight separate 16-bit or 8-bit integer additions in one cycle, instead of one floating-point addition. The Electronics and Telecommunications Research Institute (ETRI) in South Korea has researched a 64-bit multimedia enhanced on-chip multiprocessor named Raptor, which has quad processors and shares a common Graphics Control Unit (GCU). Raptor implements multimedia support directly on the processor using specialized instructions, GCU Instructions, which are variant of VIS instructions, and hardware supports. Each processor of Raptor executes multimedia applications independently and the independent streams or threads of multimedia instructions compute for and share a single GCU. The major theme of this thesis is to design the GCU architecture and to simulate it. The GCU can simultaneously execute the independent instruction streams from four General Processors (GP) and resolves the dependencies among the instructions dynamically.
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