ASIC design, implementation and anaylsis of a scalable high-radix Montgomery Multiplier Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/6682x7455

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  • Modular multiplication is a widely used operation in cryptography. Several well-known applications, such as the decipherment operation of the RSA algorithm, the Diffie-Hellman key exchange algorithm, as well as some applications currently under development, such as the Digital Signature Standard and elliptic curve cryptography, all use modular multiplication and modular exponentiation. The second operation is often implemented by a series of multiplications and additions. Multipliers implemented in hardware are generally faster than the software solutions. A small speed up for a single multiplication operation can lead to a substantial speed up for the cryptographic application. Beyond any doubt, cryptographic algorithms will be embedded in almost any exchanging of information. Applications, such as smart cards and hand-helds require hardware designs restricted on area and power resources. Other applications require fast computation with almost no area restrictions. It is important that a designer has the opportunity to make the area versus computational time trade-off. An aspect of cryptographic applications is that very large numbers are used and also the numbers' bit-size can vary. The bit-size range varies from 128 and 256 bits for elliptic curve cryptography to 1024 and 2048 bits for applications based on exponentiation. Most of the hardware designs for modular multiplication are fixed-precision solutions. That is, the operands can be only of fixed bit-size. Designs that can take operands with an arbitrary precision are been researched in the ASIC and the FPGA realms. A scalable multiplier operates on any bit-size of the input values. The maximal bit-size must be known at design time. However, any bit-size less than the maximal one can be handled the multiplier. High-radix multipliers exhibit higher complexity of the design. This thesis shows that for certain hardware architectures this higher complexity does not degrade the benefits of using higher radices for computation. The Montgomery Multiplication algorithm provides the advantage that the division step in taking the modulus is replaced by bit-shifting, an easy to implement in hardware operation. The goal of this thesis work is to describe and analyze three hardware solutions for a scalable (variable-precision) High-radix Montgomery multiplication. Each solution has different area consumption and yields different computational times. A Radix-2 design is described and two Radix-8 designs are proposed. The three are analyzed and compared with other hardware and software designs. The effect of higher precision of the computation is analyzed.
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