Graduate Thesis Or Dissertation


Dynamic Error Calibration for Continuous-Time Delta-Sigma Modulator with Multi-GHz Sampling Rate Public Deposited

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  • Continuous-time ΔΣ modulators are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requirements while maintaining good power efficiency, multi-bit feedback is typically used. This approach provides benefits such as lower OSR, relaxed loop filter requirements, and reduced jitter sensitivity. However, at multi-GHz clock rates, dynamic errors introduced by inter-symbol interference in a multi-bit feedback DAC become pronounced, thereby degrading SFDR and reducing blocker tolerance. Several methods to minimize ISI have been previously reported; however, they require complex circuitry and introduce significant excess loop delay, or require a single-bit DAC. In this work, an energy-efficient analog-based ISI mitigation scheme is implemented. It introduces only negligible additional ELD, requires minimal extra circuitry, significantly improves SFDR, and can be used with a multi-bit NRZ DAC. Fabricated in 28nm CMOS, the prototype dissipates 64.3mW. It achieves 95.2dB SFDR and 79.8dB SNDR over 50MHz BW sampled at 2GHz.
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