A DSP controlled multi-level inverter providing DC-link voltage balancing, ride-through enhancement and common-mode voltage elimination Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/6m311s498

Descriptions

Attribute NameValues
Creator
Abstract or Summary
  • With the development of high performance power electronic and semiconductor technologies, Adjustable Speed Drive (ASD) systems are increasingly applied in residential, commercial and industrial applications. Due to the advantages at higher power ratings, the three-level Neutral-Point-Clamped (NPC) Voltage Source Inverter (VSI) is being employed in industrial and traction applications, static VAR compensation systems, active filtering and utility interconnection applications. The NPC-VSI is suitable for high voltage and high power applications due to the use of series-connected switching devices. Furthermore, Electro Magnetic Interference (EMI) and the voltage stress across the inverter switches and load can be reduced because of increased levels of the output voltages compared with the conventional 2-level inverters. However, an excessively high voltage may be applied to switching devices if the Neutral-Point (NP) voltage varies from the center voltage of the dc-bus voltage. This is the inherent problem caused by the unbalanced switching states of the NPC inverter. In addition, common-mode voltages may be generated by the NP voltage variation. In response to these drawbacks, various strategies including carrier-based PWM schemes and Space Vector Modulation (SVM) based PWM schemes have been proposed to balance the NP voltage. All the above methods can operate successfully under given operating conditions, but they do result in limitations in the performance. The major objective of this research is to investigate and enhance the application issues of the NPC-VSI including balancing the dc-bus voltage, in addition to reducing the common-mode voltage and improving the ride-through ability. Therefore, analysis of the NP voltage generation is presented and existing NP voltage balancing techniques are evaluated. It is found that common-mode voltage cancellation and NP voltage control are difficult to be realized at the same time, by the arithmetic methods. Thus, a hardware method to keep the NP voltage balanced is proposed and implemented while the mitigation of common-mode voltage is being implemented by an arithmetic method. In addition, the ride-through ability is also enhanced through the proposed topology. Correlation of the simulation and experimental results are provided.
Resource Type
Date Available
Date Issued
Degree Level
Degree Name
Degree Field
Degree Grantor
Commencement Year
Advisor
Committee Member
Academic Affiliation
Non-Academic Affiliation
Subject
Rights Statement
Language
Replaces
Additional Information
  • description.provenance : Approved for entry into archive by Linda Kathman(linda.kathman@oregonstate.edu) on 2009-01-27T14:32:00Z (GMT) No. of bitstreams: 1 Shaoan_Dai.pdf: 2800972 bytes, checksum: e5475b742e4e726c67a60cef1b2d6159 (MD5)
  • description.provenance : Submitted by Philip Vue (vuep@onid.orst.edu) on 2009-01-26T23:24:21Z No. of bitstreams: 1 Shaoan_Dai.pdf: 2800972 bytes, checksum: e5475b742e4e726c67a60cef1b2d6159 (MD5)
  • description.provenance : Made available in DSpace on 2009-01-27T14:32:01Z (GMT). No. of bitstreams: 1 Shaoan_Dai.pdf: 2800972 bytes, checksum: e5475b742e4e726c67a60cef1b2d6159 (MD5)
  • description.provenance : Approved for entry into archive by Linda Kathman(linda.kathman@oregonstate.edu) on 2009-01-27T14:28:40Z (GMT) No. of bitstreams: 1 Shaoan_Dai.pdf: 2800972 bytes, checksum: e5475b742e4e726c67a60cef1b2d6159 (MD5)

Relationships

In Administrative Set:
Last modified: 08/19/2017

Downloadable Content

Download PDF
Citations:

EndNote | Zotero | Mendeley

Items