With the development of high performance power electronic and semiconductor technologies, Adjustable Speed Drive (ASD) systems are increasingly applied in residential, commercial and industrial applications. Due to the advantages at higher power ratings, the three-level Neutral-Point-Clamped (NPC) Voltage Source Inverter (VSI) is being employed in industrial and traction applications, static VAR compensation systems, active filtering and utility interconnection applications.
The NPC-VSI is suitable for high voltage and high power applications due to the use of series-connected switching devices. Furthermore, Electro Magnetic Interference (EMI) and the voltage stress across the inverter switches and load can be reduced because of increased levels of the output voltages compared with the conventional 2-level inverters. However, an excessively high voltage may be applied to switching devices if the Neutral-Point (NP) voltage varies from the center voltage of the dc-bus voltage. This is the inherent problem caused by the unbalanced switching states of the NPC inverter. In addition, common-mode voltages may be generated by the NP voltage variation. In response to these drawbacks, various strategies including carrier-based PWM schemes and Space Vector Modulation (SVM) based PWM schemes have been proposed to balance the NP voltage. All the above methods can operate successfully under given operating conditions, but they do result in limitations in the performance.
The major objective of this research is to investigate and enhance the application issues of the NPC-VSI including balancing the dc-bus voltage, in addition to reducing the common-mode voltage and improving the ride-through ability. Therefore, analysis of the NP voltage generation is presented and existing NP voltage balancing techniques are evaluated. It is found that common-mode voltage cancellation and NP voltage control are difficult to be realized at the same time, by the arithmetic methods. Thus, a hardware method to keep the NP voltage balanced is proposed and implemented while the mitigation of common-mode voltage is being implemented by an arithmetic method. In addition, the ride-through ability is also enhanced through the proposed topology. Correlation of the simulation and experimental results are provided.