Random dopants and low-frequency noise reduction in deep-submicron MOSFET technology Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/73666717j

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  • The future of mixed-signal, memory, and microprocessor technologies are dependent on ever increasing analog and digital integration, higher cell densities, and demand for more processing power. As a result MOSFET device dimensions continue to shrink to meet these demands. A side effect of device scaling is increased variability at each technological node which affects both analog and digital circuits in terms of decreased yields, performance, and noise margins. At deep sub-micron dimensions the Low-Frequency Noise (LFN) of the MOSFET is dominated by the influence of one or more active traps capturing and emitting charge to and from the oxide creating wide variations in the LFN from otherwise identical devices. Additionally, the random position of dopant atoms near the Si/SiO₂ interface create a potential landscape that induces regions of high and low conductivity which in turn causes a situation where the current is no longer uniform in the device, but consist of individual current paths or percolating currents. The coupling between the random variation of the percolation current and active traps in the oxide are responsible for the large spread ( > 3 orders of magnitude) in the noise characteristics observed in deep sub-micron MOSFET devices. The compact LFN model presented here accounts for the action of traps on percolating currents in deep-sub-micron and nano-scale MOSFETs. Two schemes for reduction of LFN are studied based on the smoothing of the surface potential. First, noise reduction is demonstrated with measurements on sub-micron MOSFETs with forward substrate bias. Secondly, the model is further verified through the reduction of noise by the removal of dopant atoms near the Si/SiO₂ interface of the device. Both schemes result in a lower noise and threshold device. Finally, these experimental findings are applied to a 2.2μm 2 MP CMOS image sensor. From the temporal noise measurements on threshold implant process splits, the image sensor noise has been significantly reduced as a direct result of fundamentals described by this MOSFET LFN model and further proves the validity of these findings.
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