Graduate Thesis Or Dissertation

 

Design techniques for low power high speed successive approximation analog-to-digital converters Public Deposited

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/73666739k

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  • This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the DACs in this ADC is more than 50% less than the conventional time-interleave ones. Several switching techniques are implemented to alleviate the impact from the parasitic capacitance and improve the performance. The pipeline SAR ADC with resistive DACs overcomes the influence from the parasitic capacitance with negligible static power consumption on the resistive DACs. Also, the complicated switching techniques can be avoided to simplify the timing logic. To verify the above two architectures, two chips were designed and fabricated in 40nm CMOS process. Finally, a new architecture of multi-step capacitive-splitting SAR ADC is proposed for low power applications. By using two identical capacitor-splitting capacitor arrays, the switching power and capacitor area can be reduced significantly.
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  • description.provenance : Approved for entry into archive by Laura Wilson(laura.wilson@oregonstate.edu) on 2013-07-22T23:27:41Z (GMT) No. of bitstreams: 2 license_rdf: 1223 bytes, checksum: d127a3413712d6c6e962d5d436c463fc (MD5) LinJiaming2013.pdf: 3197352 bytes, checksum: e5dad6fa1d725fbec56457e9ba305654 (MD5)
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  • description.provenance : Made available in DSpace on 2013-07-22T23:27:41Z (GMT). No. of bitstreams: 2 license_rdf: 1223 bytes, checksum: d127a3413712d6c6e962d5d436c463fc (MD5) LinJiaming2013.pdf: 3197352 bytes, checksum: e5dad6fa1d725fbec56457e9ba305654 (MD5) Previous issue date: 2013-07-08

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