Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as digital signal processing could be used to compensate for analog inaccuracies. Calibration assisted analog-to-digital converters(ADCs), software defined radio, digital phase locked loops, etc... have all gained from improvements in the digital processing available on chip. This thesis focusses on data converters which utilize the above features of modern day CMOS processes.
The thesis is primarily divided into two parts. The first part focuses on a technique to convert the time information into a digital word. A high resolution time-to-digital converter (TDC) architecture is proposed which combines the principles of noise-shaping integrating quantizer and charge-pump to build a third-order delta-sigma TDC using a dedicated feedback DAC. Fabricated in a 0.13µm CMOS process, the prototype TDC achieves better than 71dB DR for a 2.8MHz signal bandwidth.
The second part of the thesis proposes a blind digital calibration technique to remove non-linearity in any traditional ADC architectures. The proposed technique uses the concept of downsampling and orthogonality of sinusoidal waves to estimate the harmonic distortion in ADCs and can be used to calibrate multiple harmonics simultaneously. As a proof of concept, the algorithm is demonstrated on a first-order ring oscillator based delta-sigma ADC, whose performance is harmonic distortion limited. Built in 0.13µm CMOS process, the algorithm improves the SNDR of the ADC by 39dB while improving SFDR by 45 dB.