CMOS analog design using a digital gate array Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/8623j1076

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  • The core area of a conventional CMOS digital gate array consists of only one size of NMOS device and one size of PMOS device. Both primitives have fixed minimum channel lengths, and this has significantly impeded analog applications. This work has shown that by forming series and parallel interconnections between device primitives, the composite structure approximates a MOSFET of larger channel length and width. Thus, this simple configuration removes the constraints caused by the fixed channel length and width. Using this technique, designs for all of the basic analog building blocks such as inverters, current mirrors, source followers, and various other amplifiers have shown excellent performance. As an example, using a 3-μm CMOS technology, a folded-cascode amplifier and its associated DC biasing circuitry were designed using the digital gate array.
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  • File scanned at 300 ppi (Monochrome) using ScandAll PRO 1.8.1 on a Fi-6670 in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-07-16T15:42:31Z (GMT) No. of bitstreams: 1 LiuTianChen1988.pdf: 648910 bytes, checksum: f201b56792d9f4bb8cdf8a0f4c118dc6 (MD5)
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