Low-power video decoding with dynamic voltage scaling

Graduate Thesis Or Dissertation

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Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/8p58ph188

Descriptions

Attribute Name	Values
Creator	Dixit, Reshma
Abstract	This thesis investigates Dynamic Voltage Scaling (DVS) techniques to lower power consumption in video decoding. A DVS scheme called the Frame-data Computation Aware (FDCA) method has been presented. This method is adaptable not only to stored video applications but also to real-time video scenarios. Unlike DVS schemes for video decoding proposed earlier, the FDCA scheme does not require any preprocessing mechanisms. Results from simulations performed using the scheme are presented and compared with prior existing DVS schemes. The results indicate that the FDCA method provides power saving of up to an average of about 68%.
License	All rights reserved
Resource Type	Masters Thesis
Date Available	2009-05-18T22:48:03+00:00
Date Issued	2004-04-08
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	2004
Advisor	Lee, Ben
Academic Affiliation	Electrical Engineering and Computer Science
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Image processing -- Digital techniques Electric power -- Conservation Voltage regulators Video compression
权利声明	In Copyright
Publisher	Oregon State University
Language	English [eng]
Replaces	http://hdl.handle.net/1957/11602

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