A comparative study between sinusoidal and squarewave clocking for alleviating the jitter limitation in multi-gigaHertz ADCs Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/9k41zk08k

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  • Abstract: Various applications like wireless UWB communication, fast data acquisition systems and digital storage oscilloscopes needs ADCs with instantaneous input signal bandwidth from 0.1-40 GigaHertz range with 6-10 bits of resolution -- a challenging task and an impressive goal to achieve. Flash ADCs have been conventionally employed to achieve these goals but have been proved to be power hungry and ineffective for higher resolution. Time-interleaved converters are another option that relax the device speed and circuit complexity. Current research shows that at high input frequencies in the MultiGigaHertz range, the performance of these time-interleaved high speed ADCs is limited mainly by the sampling clock jitter. In this work, the effect of clock jitter on the data acquisition for a sampled data system is analyzed and discussed. Under the premise that, for a given jitter specification, it is relatively easy to generate a clean high frequency sinusoidal signal than a high frequency squarewave signal, this proposed work makes use of a clean sinusoid as the sampling clock. This high frequency sinusoidal clock, embedded with low frequency squarewave clocks, is employed in a proposed bottom plate sampling Track-and-Hold (T/H) architecture with the aim of improving the SNR at multi-GigaHertz frequencies. A comparative study on the performance of this T/H circuit (SNDR,ENOB) for sinusoidal sampling and conventional squarewave sampling is presented. The work concludes that for high frequency sampled data acquisition system, where sampling clock with sub-1ps jitter values are needed, the presented scheme of sinusoidal sampling is advantageous for reducing sampling clock uncertainty when compared against the conventional squarewave sampling technique.
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