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A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's Public Deposited

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  • A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate the methodology and simulation results. Substrate noise coupling from a large-scale digital processor to simple analog circuits for two different designs with the same functionality has been analyzed. Compared to existing methodologies there is a speedup Of over 80 times with one-tenth the memory use is obtained with only a 5 percent loss in accuracy. This allows for the rapid identification of major noise injection mechanisms and solutions for their reduction.
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